The present invention relates to an electrostatic discharge (ESD) protection configuration for signal inputs and outputs with overvoltage tolerance in, in particular, CMOS circuits, having an NMOS transistor which is configured as an ESD protection element and is connected to an I/O (input/output) pad (or contact pad) of the CMOS circuit.
In modern CMOS technology, components are configured for low operating voltages of 1.8 V or less in order, in the case of such optimized components, to keep the power loss thereof low, to obtain a higher packing density for them and, finally, also to achieve greater rapidity of individual transistors through smaller geometrical dimensions. Such optimization of the components in CMOS technology can be achieved without a relatively high outlay and affords considerable advantages, as has been indicated.
However, it cannot be avoided that many of the CMOS circuits realized in this technology also have to be used in electrical environments in which signals with higher voltages of, for example, 3.3 V or 5 V arise on these circuits. For this reason, in the case of such CMOS circuits, it is necessary to guarantee a higher dielectric strength in the I/O region than in their core region.
Since the gate oxide of CMOS transistors is damaged by voltages higher than nominal voltages, usually the voltage which is permitted to occur as a maximum across the gate oxide of the CMOS transistors used, taking account of the lifetime specified therefore, quite generally has a limiting effect.
In order to obtain a higher dielectric strength in the I/O region, two fundamentally different possibilities are initially conceivable. On the one hand, it is possible to use additional I/O transistors with a larger gate oxide thickness. However, this leads to the fabrication process being made considerably more expensive, so that this possibility is to be regarded as less economic. On the other hand, it is possible to use particular circuitry measures for, for example, inverters or output drivers of the CMOS circuit, such as, for example, stacking of NMOS transistors and driving of the well of a PMOS transistor, which is also referred to as a xe2x80x9cfloating wellxe2x80x9d. In practice, the concept of the xe2x80x9cstackedxe2x80x9d NMOS and of the xe2x80x9cfloating wellxe2x80x9d PMOS as ESD protection has scarcely gained any acceptance since it leads to a reduction of the ESD performance, that is to say specifically to a lower ESD strength and a higher clamping voltage.
Solution approaches that have been described hitherto in the technical literature for the above problem of a higher dielectric strength in the I/O region of CMOS circuits use a series circuit of NMOS transistors (see the reference by W. Anderson, D. Krakauer, titled EOS/ESD Symp. Proc., 1998, pp. 54-62) which are configured as ESD protection elements. However, such a series circuit often reduces the ESD performance with regard to the ESD strength of the corresponding ESD protection element and the voltage limiting in the high-current range, resulting in a reduced protection effect.
Thick oxide transistors, which are based on shallow trench isolation in modern CMOS technology, have a poor ESD strength and are scarcely taken into consideration as protection elements in technologies other than in LOCOS. As an alternative, it is also possible to use substrate-triggered lateral NPN transistors. However, in the technical literature, these are only discussed in connection with epitaxy processes (see the reference by J. Smith, titled EOS/ESD Symp. Proc., 1998, pp. 63-71).
It is accordingly an object of the invention to provide an ESD protection configuration for signal inputs and outputs with an overvoltage tolerance which overcomes the above-mentioned disadvantages of the prior art devices of this general type, which allows the I/O region of CMOS circuits to be protected against overvoltages in a simple manner and with a high ESD performance.
With the foregoing and other objects in view there is provided, in accordance with the invention, a combination of a CMOS circuit having an input/output pad and a low supply voltage terminal conducting a low supply voltage, and an electrostatic discharge (ESD) protection configuration for signal inputs and outputs with an overvoltage tolerance for the CMOS circuit. The ESD protection configuration includes an NMOS transistor having a gate and functioning as an ESD protection element connected between the input/output pad and the low supply voltage terminal. The NMOS transistor has a channel with a corresponding doping or lightly doped regions formed in the channel resulting in a high threshold voltage of about 2 V being obtained. A voltage divider is connected to the input/output pad and applies an increased voltage of about 1 V to the gate. The voltage divider contains a parallel circuit formed by a capacitor connected in parallel with a resistor.
In the case of an ESD protection configuration of the type mentioned in the introduction, the object is achieved according to the invention by virtue of the fact that the NMOS transistor is connected between the I/O pad and the low supply voltage. The NMOS transistor has a high threshold voltage requiring an increased voltage to be applied to the gate of the NMOS transistor.
Thus, in the case of the ESD protection configuration according to the invention, an NMOS transistor having a high threshold voltage, which may be about 2 V, is used as the central ESD protection element. An increased voltage, of 1 V for example, is required to be applied to gate of the NMOS transistor. In this case, no relevant leakage current occurs. As a result of the bias voltage at the gate, however, the voltage drop across the gate oxide to the drain side of the NMOS transistor decreases correspondingly.
The increase in the threshold voltage of the NMOS transistor can be achieved by a suitable doping of its lightly doped (LDD) regions as now described. By way of example, the n+-conducting source zone and the n+-conducting drain zone are provided with a pldd-implantation instead of an nldd implantation (pldd=lightly p-doped; nldd=lightly n-doped) in their respective region adjoining the channel beneath the gate electrode.
Another possibility for increasing the threshold voltage relates to introducing an additional channel doping, for example by implantation, in the channel region between the source zone and the drain zone, so that there is an increased p-type doping concentration here in the case of n+-doped source and drain zones.
Both of the possibilities mentioned above, mainly a suitable doping of the LDD regions and a corresponding channel doping, can be realized relatively simply. In particular, the replacement of nldd by pldd in the LDD regions can be realized without an additional process step. This is true irrespective of whether or not an epitaxy technology is used to realize the ESD protection configuration.
Finally, in the case of the ESD protection configuration according to the invention, the circuitry of the gate of the NMOS transistor does not pose any problems either. The bias voltage for a gate of 1 V, for example, can be derived from a voltage, such as a bandgap voltage for example, generated in the CMOS circuit. Another possibility is to incorporate between the I/O pad and the low supply voltage a high-impedance voltage divider, for example using a PNP transistor.
Although the ESD protection configuration according to the invention is preferably used in CMOS circuits, it can also be used in the case of other components, such as, for example, thyristors based on NMOS transistors.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an ESD protection configuration for signal inputs and outputs with an overvoltage tolerance, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.